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be word wise barrel shifted towards the least significant word. Accessing the KEY registers are done in
the same fashion through KEYLn and KEYHn. See Figure 27.3 (p. 382) . Note that KEYHA, KEYHB,
KEYHC and KEYHD are really the same register, just mapped to four different addresses. You can
then chose freely which of these addresses you want to use to update the KEY7-KEY4 registers. The
same principle applies to the KEYLn registers. Mapping the same registers to multiple addresses like
this, allows the DMA controller to write a full 256-bit key in one sweep, when incrementing the address
between each word write.
Figure 27.3. AES Data and Key Register Operation
Shift on write and read
Write data
AES_DATA/
AES_XORDATA
DATA3
DATA2
DATA1
DATA0
Read data
Shift on write and read
Write data
AES_KEYLn
KEY3
KEY2
KEY1
KEY0
Read data
Shift on write and read
Write data
AES_KEYHn
KEY7
KEY6
KEY5
KEY4
Read data
27.3.2.1 Key Buffer
When encrypting multiple blocks of data in a row, the PlainKey must be written to the key register
between each encryption, since the contents of the key registers will be turned into the CipherKey during
the encryption. The opposite applies when decrypting, where you have to re-supply the CipherKey
between each block. However, in AES128 mode, KEY4-KEY7 can be used as a buffer register, to hold
an extra copy of the KEY4-KEY0 registers. When KEYBUFEN is set in AES_CTRL, the contents of
KEY7-KEY4 are copied to KEY4-KEY0, when an encryption/decryption is started. This eliminates the
need for re-loading the KEY for every encrypted/decrypted block when running in AES128 mode.
27.3.2.2 Data Write XOR
The AES module contains an array of XOR gates connected to the DATA registers, which can be used
during a data write to XOR the existing contents of the registers with the new data written. To use the
XOR function, the data must be written to AES_XORDATA location.
Reading data from AES_XORDATA is equivalent to reading data from AES_DATA.
27.3.2.3 Start on Data Write
The AES module can be configured to start an encryption/decryption when the new data has been written
to AES_DATA and/or AES_XORDATA. A 2-bit counter is incremented each time the AES_DATA or
AES_XORDATA registers are written. This counter indicates which data word is written. If DATASTART/
XORSTART in AES_CTRL is set, an encryption will start each time the counter overflows (DATA3 is
written). Writing to the AES_CTRL register will reset the counter to 0.
27.3.3 Interrupt Request
The DONE interrupt flag is set when an encryption/ decryption has finished.
27.3.4 DMA Request
The AES module has 4 DMA requests which are all set on a finished encryption/decryption and cleared
on the following conditions:
? DATAWR: Cleared on a AES_DATA write or AES_CTRL write
? XORDATAWR: Cleared on a AES_XORDATA write or AES_CTRL write
? DATARD: Cleared on a AES_DATA read or AES_CTRL write
2011-04-12 - d0001_Rev1.10
382
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